The present invention relates to a method of manufacturing a transistor, and more particularly, to an improved method of manufacturing an inverse-T shaped transistor.
FIG. 1 shows the structure of a common conventional metal oxide semiconductor field effect transistor (MOSFET).
Referring to FIG. 1, the above MOSFET is composed of a gate insulating film 2 such as a silicon oxide film formed on a p-type silicon substrate 1, a gate electrode 3 (e.g., an impurity-doped polysilicon) formed on gate insulating film 2, a gate cap oxide film 4 (e.g., a silicon oxide film) formed on gate electrode 3, an n.sup.+ type source region 5 formed on the left side of gate electrode 3 in p-type silicon substrate 1, and an n.sup.+ type drain region 6 formed on the right side of gate electrode 3 in p-type silicon substrate 1.
In FIG. 1, if a gate voltage V.sub.G is applied to gate electrode 3, electrons move from source region 5 to drain region 6.
However, at this time, as shown in FIG. 1, since p-type silicon substrate 1 has a high potential and n.sup.+ type drain region 6 has a very low potential, a strong electric field is formed at the point "a". Therefore, electrons surge toward the point "a", so that gate oxide film 2 is liable to crack. The electrons trapped in gate electrode 3 are combined with holes there, causing the gate voltage V.sub.G to be lowered.
Accordingly, since the fixed gate voltage V.sub.G is not precisely applied, the characteristics of the MOSFET are deteriorated.
The phenomenon that electrons surge in the point "a" as described above is called the hot carrier effect.
As is well known, in order to reduce the hot carrier effect, that is, to relieve the drastic variation of the potential near the point "a" in n.sup.+ type drain region 6, there has been suggested using a lightly doped drain (LDD) MOSFET comprising source and drain regions of LDD structure.
In the LDD MOSFET, the drain region, which includes only a high concentration n-type (n.sup.+) region in the conventional MOSFET, is divided into a low concentration n-type (n.sup.-) region and a high concentration n-type (n.sup.+) region).
Therefore, a gentle variation of the potential can be obtained at the interface between the p-type substrate and n-type drain region.
In other words, it is possible to prevent a strong electric field from being formed at the above interface.
Hereinafter, a method of manufacturing a conventional LDD MOSFET will be described with reference to FIGS. 2a to 2d.
As shown in FIG. 2a, a silicon oxide film 12 for use as a gate insulating film is formed on a p-type silicon substrate 11 according to a thermal oxidation method. A polysilicon film 13 (doped with impurity) for use as a gate electrode is deposited on silicon oxide film 12 according to a chemical vapor deposition (CVD) method.
Thereafter, a silicon oxide film 14 for use as a gate cap insulating film is deposited on polysilicon film 13 using a CVD method.
A photo-lithography process is performed on silicon oxide film 14, thereby defining a gate electrode region. Silicon oxide film 14, polysilicon film 13 and silicon oxide film 12 are dry-etched simultaneously, thereby forming gate insulating film 12a, gate electrode 13a and gate cap insulating film 14a, as shown in FIG. 2b.
Then, using gate cap insulating film 14a as an ion-implantation mask, impurity ions of low concentration n-type (n.sup.- type) are implanted in a direction perpendicular to the substrate surface. As a result, n.sup.- type source region 15a and n.sup.- type drain region 15b are formed on opposite sides of gate electrode 13a in p-type silicon substrate 11.
Thereafter, as shown in FIG. 2c, a silicon oxide film for use as a gate sidewall spacer is deposited through a CVD method. A reactive ion etching (RIE) process is performed on the silicon oxide film, thereby forming sidewall spacers 16a and 16b on opposite sidewalls of gate insulating film 12a, gate electrode 13a and gate cap insulating film 14a.
Then, using gate cap insulating film 14a and sidewall spacers 16a and 16b as ion-implantation masks, impurity ions of high concentration n-type (n.sup.+ type) are implanted in the direction perpendicular to the substrate surface. As a result, n.sup.+ type source region 17a and n.sup.+ drain region 17b are formed on both sides of sidewall spacers 16a and 16b in p-type silicon substrate 11.
As shown in FIG. 2d, after depositing an insulating film 18 through a CVD method, a photo-lithography process and a dry-etching process are performed, thereby forming a source contact hole, a gate contact hole and a drain electrode contact hole at n.sup.+ source region 17a, gate electrode 13a and n.sup.+ drain region 17b, respectively.
Thereafter, a metal film is deposited through a CVD method so as to completely fill the above contact holes. A photo-lithography process and a dry-etching process are then performed on the metal film, thereby forming source contact electrode 19a, gate contact electrode 19b and drain contact electrode 19c.
However, the following problems remain in the MOSFET having the above LDD structure.
First, due to the additional formation of the n.sup.- type drain region, even if the electric field is reduced at the interface between the drain region 17b and the gate insulating film 12a, gate voltage V.sub.g is not applied to the bottom of the sidewall spacer since no gate electrode is formed there.
Accordingly, a strong electric field is still formed in the interface between the drain region and the gate insulating film, and results in generation of the hot carrier effect.
Second, since the source region and drain region have an LDD structure, that is, they are formed with a double-structure of a low concentration region and a high concentration region, the source and drain regions have high resistance. Therefore, current flow is reduced as a result of the high resistance.
Third, in order to form the source and drain regions with an LDD structure, a masking process and an ion-implantation process are required to be formed twice. Therefore, the process is complicated.
In order to solve the above described first problem of the LDD MOSFET, there was suggested an inverse-T shaped MOSFET structure.
A prior art method of manufacturing the inverse-T shaped MOSFET will be described with reference to FIGS. 3a to 3f.
This method of manufacturing the inverse-T shaped MOSFET is disclosed in U.S. Pat. Nos. 4,907,048 and 4,963,054.
As shown in FIG. 3a, an oxide film 22 is grown on a p-type silicon substrate 21 as a thin gate insulating film. A polysilicon layer 23 and an oxide film 24 are deposited sequentially on gate oxide film 22, and then a photoresist is coated on oxide film 24. A photolithography process is performed on photoresist 25, thereby forming a photoresist pattern 25 for defining a gate region.
As shown in FIG. 3b, using the photoresist pattern 25 as an etch-mask, oxide film 24 is etched, and successively, polysilicon film 23 is etched to a predetermined depth from the surface thereof. Then, photoresist pattern 25 is removed. As a result, polysilicon pattern 23a and gate cap oxide film 24a are formed.
As shown in FIG. 3c, n-type impurity ions are implanted at a low concentration, thereby forming n.sup.- type source region 26 and n.sup.- type drain region 27.
As shown in FIG. 3d, according to a CVD method, an oxide film is deposited on the entire exposed surface of the exposed resultant structure and the oxide film is etched through an RIE method, thereby forming sidewall spacers 28a and 28b on opposite sides of polysilicon pattern 23a.
As shown in FIG. 3e, using gate cap insulating film 24a and sidewall spacers 28a and 28b as etch-masks, the exposed portion of polysilicon pattern 23a is etched, thereby forming an inverse-T shaped gate electrode 23b.
As shown in FIG. 3f, using gate cap insulating film 24a and sidewall spacers 28a and 28b as ion-implantation masks, n-type impurity ions are implanted at a high concentration, thereby forming an n.sup.+ type source region 29 and an n.sup.+ type drain region 30 in n.sup.- type source region 26 and n.sup.- type drain region 27, respectively.
That is, with regard to the feature of using sidewall spacers, the above described method is the same as that of the LDD MOSFET structure of FIG. 2. However, the above described method is different from that of the LDD MOSFET of FIG. 2 because the gate electrode extends to the bottom of the sidewall spacer.
In the inverse-T shaped LDD MOSFET manufactured as described above, n.sup.- type source region 26 and n.sup.- type drain region 27 are fully overlapped with gate electrode 23b so that they are affected by the gate voltage V.sub.G. Therefore, immunity against the hot carrier effect can be improved.
However, as known in the above-described manufacturing method, in order to form the inverse-T shaped gate electrode after forming the polysilicon layer, when the polysilicon layer is etched to a predetermined depth, it is difficult to precisely control the etch-stop endpoint for stopping the etching process.
Further, in order to make the inverse-T shaped gate electrode, an additional etching process using the sidewall spacer as an etch-mask is required. Therefore, the process is complicated.